
            Western Digital FD179X series Floppy Disk Controller
            ====================================================


GENERAL DESCRIPTION
===================

The FD179X are n-channel silicon gate MOS LSI devices which perform the
functions of a floppy disk controller/formatter in a single chip
implementation.  The FD179X, which can be considered the end result of both
the FD1771 and FD1781 designs, is IBM 3740 compatible in single density mode
(FM) and System 34 compatible in double density (MFM).  The FD179X contains
all the features of its predecessor the FD1771, plus the added feature
necessary to read/write and format a double density diskette.  These include
address mark detection, FM and MFM encode and decode logic, window
extension, and write precompensation.  In order to maintain compatibility,
the FD1771, FD1781 and FD179X designs were made as close as possible with
the computer interface, instruction set, and I/O registers being identical.
Also, head load control is identical.  In each case, the actual pin
assignments vary by only a few pins from any one to another.

The processor interface consists of an 8-bit bi-directional bus for data,
status, and control word transfers.  The FD179X is set up to operate on a
multiplexed bus with other bus-oriented devices.

The FD179X is TTL compatible on all inpus and outputs.  The outputs will
drive one TTL load, or three LS loads.  The 1793 is identical to the 1791
except the DAL lines are TRUE for systems that utilize true data busses.

The 1795/7 has a side select output for controlling double sided drives, and
the 1792 and 1794 are "Single Density Only" versions of the 1791 and 1793
respectively.  On these devices, the DDEN pin must be left open.


PROCESSOR INTERFACE
===================

The interface to the processor is accomplished through the eight data access
lines (/DAL) and associated control signals.  The /DAL are used to transfer
Data, Status, and Control words out of, or into the FD179X.  The /DAL are
three state buffers that are enabled as output drivers when Chip Select
(/CS) and Read Enable (/RE) are active (low logic state) or act as input
receivers when /CS and Write Enable (/WE) are active.

When transfer of data with the FDC is required by the host processor, the
device address is decoded and /CS is made low.  The address bits A1 and A0,
combined with the signas /RE during a read operation or /WE during a write
operation are interpreted as selecting the following registers:

        Ŀ
         A1   A0   Read (/RE)          Write (/WE)      
        Ĵ
         0    0    Status Register     Command Register 
         0    1    Track Register      Track Register   
         1    0    Sector Register     Sector Register  
         1    1    Data Register       Data Register    
        

During Direct Memory Address (DMA) types of data transfers between the data
register of the FDC and the processor, the Data Request (DRQ) output is used
in data transfer control.  This signal also appears as status bit 1 during
read and write operations.

On disk read operations, the DRQ is activated (set high) when an assembled
serial input byte is transferred in parallel to the data register.  This bit
is cleared when the data register is read by the processor.  f the data
register is read after one or more characters are lost, by having new data
transferred into the register prior to processor readout, the lost data bit
is set in the status register.  The read operation continues until the end
of sector is reached.

On disk write operations, the data request is activated when the data
register transfers its contents to the data shift register, and requires a
new data byte.  It is reset when the data register is loaded with new data
by the processor.  If new data is not loaded at the time the next serial
byte is required by the flopyp disk, a byte of zeroes is written on the
diskette and the lost data bit is set in the status register.

At the completion of every command, an INTRQ is generated.  INTRQ is reset
by either reading the status register or by loading the commmand register
with a new command.  In addition, INTRQ is generated if a Force Interrupt
command condition is met.

The FDC had two modes of operation according to the state of /DDEN.  When
/DDEN is 1, single density is selected.  In either case, the CLK input is at
2 MHz.  However, when interfacing with the mini-floppy, the CLK inptu is set
at 1 MHz for both single density and double density.


COMMAND DESCRIPTION
===================

The FDC will accept eleven commands.  Command words should only be loaded in
teh command register when the busy status bit is off (Status bit 0).  The
one exception is the Force Interrupt command.  Whenever a command is being
executed, the Busy status bit is set.  When a command is completed, an
interrupt is generated, and the Busy status bit is reset.  The Status
Register indicates whether the completed command encountered an error or was
fault free.  For ease of discussion, commands are divided into four types.
Commands and types are summarized in table 1.

                          Table 1: Command Summary
       Ŀ
                                                Bits               
        Type    Command             7   6   5   4   3   2   1   0  
       Ĵ
         I      Restore             0   0   0   0   h   V   r1  r0 
         I      Seek                0   0   0   1   h   V   r1  r0 
         I      Step                0   0   1   T   h   V   r1  r0 
         I      Step-In             0   1   0   T   h   V   r1  r0 
         I      Step-Out            0   1   1   T   h   V   r1  r0 
         II     Read Sector         1   0   0   m   S   E   C   0  
         II     Write Sector        1   0   1   m   S   E   C   a0 
         III    Read Address        1   1   0   0   0   E   0   0  
         III    Read Track          1   1   1   0   0   E   0   0  
         III    Write Track         1   1   1   1   0   E   0   0  
         IV     Force Interrupt     1   1   0   1   I3  I2  I1  I0 
       


                           Table 2: Flag Summary
        Ŀ
         r1 r0   See table 3 for stepping motor rate             
                                                                 
         V       0 - No Verify                                   
                 1 - Verify on destination track                 
                                                                 
         h       0 - Unload head at beginning                    
                 1 - Load head at beginning                      
                                                                 
         T       0 - No track register update                    
                 1 - Update track register                       
                                                                 
         a0      0 - FB Data Address Mark                        
                 1 - F8 DAM (Deleted data)                       
                                                                 
         C       0 - Disable side compare                        
                 1 - Enable side compare                         
                                                                 
         U       0 - Update SSO to 0                             
                 1 - Update SSO to 1                             
                                                                 
         E       0 - No 15 msec delay                            
                 1 - 15 msec delay                               
                                                                 
         S       0 - Compare for side 0                          
                 1 - Compare for side 1                          
                                                                 
         m       0 - Single record                               
                 1 - Multiple records                            
                                                                 
         Ix      Interrupt condition flags                       
         I0      1 - Not ready to ready transition               
         I1      1 - Ready to not ready transition               
         I2      1 - Index pulse                                 
         I3      1 - Immediate interrupt, requires a reset       
         I0-3    0 - Terminate with no interrupt (INTRQ)         
        


(I'm cheating and leaving out the stepping rate discussion, since you're
probably using disk images)


TYPE I COMMANDS
===============

Restore (Seek track 0)
----------------------

Upon receipt of this command, the Track 00 (/TR00) input is sampled.  If
/TR00 is active low indicating the read/write head is positioned over track
0, the track register is loaded with zeroes and an interrupt is generated.
If /TR00 is not active low, stepping pulses at a rate specified by the r1 r0
field are issued until the /TR00 input is activated.  If /TR00 does not go
active low after 255 steppign pulses, the FDC terminates operation,
interrupts, and sets the seek error status bit, providing the V flag is set.
The h bit allows the head to be loaded at the start of the command.


Seek
----

This command assumes that the track register contains the track number of
the current position of the read/write head, and the data register contains
the desired track number.  The FDC will update the track register and issue
stepping pulses in the appropriate direction until the contents of the track
register are equal to the contents of the data register (the desired track
location).  A verification operation takes place if the V flag is on.  The h
bit allows the head to be loaded at the start of the command.  An interrupt
is generated at the completion of the command.  Note:  When using multiple
drives, the track register must be updated for the drive selected before
seeks are to be issued.


Step
----

Upon receipt of this command, the FDC issues one stepping pulse to the
drive.  The stepping motor direction is the same as in the previous step
command.  After a delay determined by the r1 r0 field, a verification takes
place if the V flag is on.  If the U flag is on, the track register is
updated.  The h bit allows the head to be loaded at the start of the
command.  An interrupt is generated at the completion of the command.


Step-In
-------

Upon receipt of this command, the FDC issues one stepping pulse in the
direction towards track 76.  If the U flag is on, the track register is
incremented by one. After a delay determined by the r1 r0 field, a
verification takes place if the V flag is on.  The h bit allows the head to
be loaded at the start of the command.  An interrupt is generated at the
completion of the command.


Step-Out
--------

Upon receipt of this command, the FDC issues one stepping pulse in the
direction towards track 0.  If the U flag is on, the track register is
incremented by one. After a delay determined by the r1 r0 field, a
verification takes place if the V flag is on.  The h bit allows the head to
be loaded at the start of the command.  An interrupt is generated at the
completion of the command.


TYPE II COMMANDS
================

Type II commands are the Read Sector and Write Sector commands.  Prior to
loading the type II command into the command register, the computer must
load the sector register with the desired sector number.  Upon receipt of
the type II command, the busy status bit is set.  If the E flag = 1 (this is
the normal case) HLD is made active and HLT is sampled after a 15 msec
delay.  If teh E flag is 0, the head is loaded and HLT sampled with no 15
msec delay.  The ID field and data field format are shown on page 13.

When an ID field is located on the disk, the FDC comares the track number on
the ID field with the track register.  If there is not a match, the next
encountered ID field is read and a comparison is made again.  If there was a
match, the sector number of the ID field is comared with the sector
register.  If there is not a sector match, the next encountered ID field is
read off the disk and comparisons again made.  If the ID field CRC is
correct, the data field is then located and will be either written into or
read from depending on the command.  The FDC must find an ID field with a
Track number, Sector number, side number and CRC within four revolutions of
the disk; otherwise, the Record Not Found status bit is set (Status bit 3)
and the command is terminated with an interrupt.

Each of the type II commands contains an (m) flag which determines if
multiple records (sectors) are to be read or written, depending on the
command.  If m=0, a single sector is read or written and an interrupt is
generated at the completion of the command.  If m=1, multiple records are
read or written with the sector register internally updated so that an
address verification can occur on the next record.  The FDC will continue to
read or write multiple records and update the sector register in numerical
ascending sequence until the sector register exceeds the number of sectors
on the track, or the Force Interrupt command is loaded into the command
register, which terminates the command and generates an interrupt.

For example:  If the FDC is instructed to read sector 27 and there are only
26 on the track, the sector register exceeds the number available.  The FDC
will search for 5 disk revolutions, interrupt out, and set the Record Not
Found status bit.

The Type II commands for 1791-94 also contain side select compare flags.
When C=0, no side comparison is made.  When C=1, the LSB of the side number
is read off the ID field of the disk and compared with the contents of the
(S) flag.  If the S flag compares with the side number recorded in the ID
field, the FDC continues with the ID search.  If a comparison is not made
within 5 index pulses, the interrupt line is made active and the Record Not
Found status bit is set.


Read Sector
-----------

Upon receipt of this command, the head is loaded, the busy status bit is
set, and when an ID field is encountered that has the correct track number,
sector number, side number and a correct CRC, the data field is presented to
the computer.  The data address mark (DAM) of the data field must be found
within 30 bytes in single density and 43 bytes in double density of the last
ID field CRC byte; if not, the ID field is searched for and verified again
followed by the DAM search.  If after 5 revolutions the DAM cannot be found,
the Record Not Found status bit is set and the operation is terminated.

When the first character or byte of the data field has been shifted through
the DSR, it is transferred to the data register, and DRQ is generated.  When
the next byte is accumulated in the DSR, it is transferred to the DR and
another DRQ is generated.  If the computer has not read the previous
contents of the DR before a new character is transferred, that character is
lost and the Lost Data status bit is set.  This sequence continues until the
complete data field has been inputted to the computer.  If there is a CRC
error at the end of the data field, the CRC error status bit is set, and the
command is terminated (even if it is a multiple record command).

At the end of the read operation, the type of data address mark encountered
in the data field is recorded in bit 5 of the status register.  If this bit
is 0, a normal data mark was read.  If the bit is 1, and Deleted Data mark
was read.  (The TRS-80 uses this for directory sector stuff)


Write Sector
------------

Upon receipt of the write sector command, the head is loaded and the busy
status bit set.  The data field is located on the disk as in the read
command description.  When the ID field is located, the FDC generates a data
request (DRQ).  The FDC counts off 11 bytes in FM and 22 bytes in MFM from
the CRC field, and the Write Gate output is made active if the DRQ is
serviced (i.e. the data register has been loaded by the computer).  If DRQ
has not been serviced, the command is terminated and the Lost Data status
bit is set.  If DRQ has been serviced, the WG is made active and six (FM) or
twelve (MFM) bytes zeroes are written to the disk.  At this time the DAM is
written on the disk as determined by the a0 field of the command.  If a0 is
0 a normal DAM is written, and if 1 a Deleted DAM is written.

The FDC then writes the data field and generates DRQs to the computer. If
the DRQ is not serviced in time for continuous writing the Lost Data bit is
set and a byte of zeroes is written to the disk.  The command is not
terminated.  After the last data byte has been written on the disk, the two
byte CRC is computed internally and written on the disk followed by one byte
of logic ones (0xFF).  The WG output is then deactivated.


TYPE III COMMANDS
=================


Read Address
------------

Upon receipt of this command, the head is loaded and the busy status bit is
set.  The next encountered ID field is then read in from the disk and the
six data bytes of the ID field are assembled and transferred to the DR.  DRQ
is generated for each byte.  The six bytes of the ID field are:

  Ŀ
   Track  Side    Sector   Sector  CRC  CRC 
   Addr   Number  Address  Length   1    2  
  Ĵ
     1      2        3       4      5    6  
  

Although the CRC characters are transferred to the computer, the FDC checks
for validity and the CRC error status bit is set if there is a CRC error.
The track address of the ID field is written into the sector register so
that a comparison can be made by the user.  At the end of the operation an
interrupt is generated and the busy status bit is reset.


Read Track
----------

Upon receipt of the Read Track command, the head is loaded and the busy
status bit is set.  Reading starts with the leading edge of the first
encountered index pulse and continues until the next index pulse.  All Gap,
Header, and data bytes are assembled and transferred to the data register
and DRQs are generated for each byte.  The accumulation of bytes is
synchronized to each address mark encoutnered.  An interrupt is generated at
the completion of the command.

This command has several characteristics which make it suitable for
diagnostic purposes.  They are:  Read Gate is not activated during the
command; no CRC checking is performed; gap information is included in the
data stream; the internal side compare is not performed; and the addres mark
detector is on for the duration of the command.  Because the A.M. detector
is always on, write splices or noise may cause the chip to look for an A.M.
If an address mark does not appear on schedule, the Lost Data status bit is
set.

The ID A.M., ID field, ID CRC bytes, DAM, Data and Data CRC bytes for each
sector will be correct.  The gap bytes may be read incorrectly during write
splice time because of synchronization.


Write Track Formatting The Disk
-------------------------------

Formatting the disk is a relatively simple task when operating programmed
I/O or when operating under DMA with a large amount of memory.  Data and gap
information must be provided at the computer interface.  Formatting the disk
is accomplished by positioning the R/W head over the desired track and
issuing the Write Track command.

Upon receipt of the Write Track command, the head is loaded and the busy
status bit is set.  Writing starts with the leading edge of the first
encountered index pulse and continues until the next index pulse, at which
time the interrupt is activated.  Teh DRQ is activated immediately upon
receiveing the command, butwriting will not start until after the first byte
has been loaded into the data register.  If the DR has not been loaded by
the time the index pulse is encountered, the operation is termianted making
the device Not Busy, the Lost Data status bit is set, and the interrupt is
activated.  If a byte is not present in the DR when needed, a byte of zeroes
is substituted.

This sequence continues from one index mark to the next index mark.
Normally, whatever data pattern apears in the data register is written on
the disk with a normal clock pattern.  However, if the FDC detects a data
pattern of F5 through FE in the data register, this is interpreted as data
address marks with missing clocks or CRC generation.

The CRC generator is initialized when any data byte from F8 to FE is about
to be tranferred from the data register to the data shift register in FM or
by receipt of F5 in MFM.  An F7 pattern will generate two CRC characters in
FM or MFM.  As a consequence, the patterns F5 through FE must not appear in
the gaps, data fields, or ID fields.  Also, CRCs must be generated by an F7
pattern.

Disks may be formatted in IBM 3740 or System 34 formats with sector lengths
of 128, 256, 512 or 1024 bytes.


                      Control Bytes for Initialization
    Ŀ
     Data pattern   FM interpretation      MFM interpretation     
     in Data Reg.                                                 
    Ĵ
     00 through F4  Write with clock=FF    Write value            
     F5             Not allowed            Write A1, preset CRC * 
     F6             Not allowed            Write C2 in MFM **     
     F7             Generate 2 CRC bytes   Generate 2 CRC bytes   
     F8 through FB  Write, Clk=C7, CRC set Write value            
     FC             Write, Clk=D7          Write value            
     FD             Write, Clk=FF          Write value            
     FE             Write, Clk=C7, CRC set Write value            
     FF             Write, Clk=FF          Write value            
    


TYPE IV COMMANDS
================

The Force Interrupt command is generally used to terminate a multiple sector
read or write command, or to insure Type I status in the status register.
This command can be loaded into the command register at any time.  If there
is a current command under execution (busy status bit set) the command will
be terminated and the busy status bit reset.

The lower four bits of the command determine the conditional interupt as
follows:

    I0 - Not-ready to ready transition
    I1 - Ready to not-ready transition
    I2 - Every index pulse
    I3 - Immediate interrupt

The conditional interrupt is enabled when the corresponding bit positions of
the command are set to a 1.  The, when the condition for interrupt is met,
the INTRQ line will go high signifying that the condition specified has
occurred.  If I3-I0 are all set to zero, no interrupt will occur but any
command presently under execution will be immediately terminated.  When
using the immediate interrupt (I3=1) an interrupt will be generated
immediately and the current command terminated.  Reading the status or
writing to teh command register will not automatically clear the interrupt.
The hex D0 is the only command that will enable the immediate interrupt (hex
D8) to clear on a subsequent load command register or read status register
operation.  Follow a hex D8 command with a D0 command.

Wait 8 microseconds (MFM) or 16 microseconds (FM) before issuing a new
command after issuing a force interrupt.  Loading a new command sooner than
this will nullify the forced interrupt.

Forced interrupt stops any command at the end of an internal micro
instruction and generates INTRQ when the specified condition is met.  Forced
interrupt will wait until ALU operations in progress are complete (CRC
calculations, compares, etc.)

More than one condition may be set at a time.  If, for example, the Ready to
not ready condition (I1=1) and the Every index pulse (I2=1) are both set,
the resultant command would be hex DA.  The OR operation is performed so
that either a Ready to not ready or the next index pulse will cause an
interrupt condition.


STATUS REGISTER
===============

Upon receipt of any command, except the force interrupt command, the busy
status bit is set and the rest of the status bits are updated or cleared for
the new command.  If the force interrupt command is received when there is a
current command under execution, the busy status bit is reset and the rest
of the status bits are unchanged.  If the force interrupt is received when
there is not a current command under execution, the busy status bit is reset
and the rest of the status bits are updated or cleared.  In this case, the
status register reflects the type 1 commands.

The user has the option of reading the status register through program
control or using the DRQ line with DMA or interrupt methods.  When the data
register is read the DRQ bit in the status register and the DRQ line are
automatically cleared.  A write to the data register also causes both DRQs
to reset.

The busy bit in teh status may be monitored with a user program to determine
when a command is complete, in lieu of using the INTRQ line.  When using the
INTRQ, a busy status check is not recommended because a read of the status
register to determine the condition of busy will reset the INTRQ line.

The format of the status register varies according to the type of command
being executed.  Table 4 shows the formats.

Ŀ
Bit Type 1     Read       Read       Read       Write      Write     
    Commands   Address    Sector     Track      Sector     Track     
Ĵ
 7  Not ready  Not ready  Not ready  Not ready  Not ready  Not ready 
 6  Wrt Prot   0          0          0          Wrt Prot   Wrt Prot  
 5  Hd Loaded  0          Rec type   0          Wrt Fault  Wrt Fault 
 4  Seek Err   RecNotFnd  RecNotFnd  0          RecNotFnd  0         
 3  CRC Error  CRC Error  CRC Error  CRC Error  CRC Error  CRC Error 
 2  Track 0    Lost Data  Lost Data  Lost Data  Lost Data  Lost Data 
 1  Idx Pulse  DRQ        DRQ        DRQ        DRQ        DRQ       
 0  Busy       Busy       Busy       Busy       Busy       Busy      



Type 1 Status:
--------------

Bit 7 - This bit is set when the drive is not ready.  When reset it
indicates that the drive is ready.  This bit is an inverted copy of the
Ready input pin and logically ORed with MR.

Bit 6 - When set, indicates Write Protect is activated.  This bit is an
inverted copy of the /WRPT input.

Bit 5 - When set, indicates the head is loaded and engaged.  This bit is a
logical AND of the HLD and HLT signals.

Bit 4 - When set, the desired track was not verified.  This bit is reset to
0 when updated.

Bit 3 - CRC error was encountered in the ID field

Bit 2 - When set, indicates r/w head is positioned to track 0.  This bit is
an inverted copy of the /TR00 input.

Bit 1 - When set, indicates index mark detected from the drive.  This bit is
an inverted copy of the /IP input.

Bit 0 - When set, command is in progress.  When reset, no command is in
progress.


Status for type II and III commands:
------------------------------------

Bit 7 - Same as type I.  Type II and III commands will not execute if the
drive is not ready.

Bit 6 - On write commands: Disk is write protected.

Bit 5 - On read sector this indicates the Data Address Mark.  1 = deleted
data, 0 = normal data.  On any write, this indicates a write fault.  This
bit is reset when updated.

Bit 4 - When set, it indicates that the desired track, sector or side were
not found.  This bit is reset when updated.

Bit 3 - If bit 4 is set, an error is vound in one or more ID fields.
Otherwise, it indicates a CRC error in the data field.  This bit is reset
when updated.

Bit 2 - When set, it indicates the computer did not respond to DRQ in one
byte time.  his bit is reset to 0 when updated.

Bit 1 - Data request.  This bit is a copy of the DRQ output.  When set it
indicates the DR is full on read or empty on write.  This bit is reset to
zero when updated.

Bit 0 - When set, command is under execution.  When reset, no command is
under execution.


IBM 3740 Format - 128 bytes per sector
======================================

Show below is the IBM single density format with 128 bytes per sector.  In
order to format a diskette, the user must issue the write track command, and
load the data register with the following values.  For each byte to be
written, there is one data request.  (This is for an 8 inch disk)

    Number of           Hex value of
      bytes             byte written
    ---------           -----------------------------------
        40              FF
         6              00
         1              FC (Index mark)
        26              FF
  >   6              00
        1              FE (ID address mark)
        1              Track number
        1              Side number (00 or 01)
        1              Sector Number (01 to 1A)
        1              00 (sector length)
        1              F7 (two CRC bytes written)
       11              FF
        6              00
        1              FB (data address mark)
      128              Data (IBM uses E5)
        1              F7 (two CRC bytes written)
  >  27              FF
       247              FF **

   * Write the section in the arrows 26 times (once for each sector).
  ** Continue writing until FDC interrupts out.  Approx. 247 bytes.


IBM System 34 Format - 256 bytes per sector
===========================================

Shown below is the IBM dual density format with 256 bytes per sector.  In
order to format a diskette the user must issue the write track command and
load the data register with the following values.  For every byte to be
written, there is one data request.  (This is for an 8 inch disk)


    Number of           Hex value of
      bytes             byte written
    ---------           -----------------------------------
        80              4E
        12              00
         3              F6 (Writes C2)
         1              FC (Index mark)
        50              4E
  >  12              00
        3              F5 (Writes A1)
        1              FE (ID address mark)
        1              Track number (00 to 4C)
        1              Side number (00 or 01)
        1              Sector Number (01 to 1A)
        1              01 (sector length)
        1              F7 (two CRC bytes written)
       22              4E
       12              00
        3              F5 (Writes A1)
        1              FB (data address mark)
      256              Data (E5?)
        1              F7 (two CRC bytes written)
  >  54              4E
       598              4E **

   * Write the section in the arrows 26 times (once for each sector).
  ** Continue writing until FDC interrupts out.  Approx. 598 bytes.



Non IBM Formats
===============

Variations on the IBM formats are possible to a limited extent of the
following requirements are met:

1) Sector size must be 128, 256, 512 or 1024 bytes.

2) Gap 2 cannot be varied from the IBM format

3) 3 bytes of A1 must be used in MFM

In addition, teh index address mark is not required for operation by the
FD179X.  Gap 1, 3 and 4 lengths can be as short as 2 bytes for FD179X
operation, however PLL lock up time, motor speed variation, write-splice
area, etc. will add more bytes to each gap to achieve proper operation.  It
is recommended that the IBM format be used for highest system reliability.

  Ŀ
              Single Density     Double Density 
  Ĵ
   Gap 1      16 bytes FF        32 bytes 4E    
  Ĵ
   Gap 2 *    11 bytes FF        22 bytes 4E    
               6 bytes 00        12 bytes 00    
                                  3 bytes A1    
  Ĵ
   Gap 3 **   10 bytes FF        24 bytes 4E    
               4 bytes 00         8 bytes 00    
                                  3 bytes A1    
  Ĵ
   Gap 4      16 bytes FF        16 bytes 4E    
  

  * Gap 2 byte counts MUST be exact.
 ** Other gap byte counts are minimum, except 3 bytes of
    A1 must be written.


